1. Field of the Invention
The present invention relates generally to a digital phase locked loop, and in particular to a digital phase locked loop that generates a frequency modulated output clock.
2. Description of the Related Art
Phase locked loops (PLL) have been widely used in communication systems or the like, some frequently appearing in applications such as extracting information from carrier waves or synchronous signals. A phase locked loop is a well-known clock synchronization technique to drive a timing signal, synchronized or locked, to a reference clock signal.
A PLL is a frequency-selective circuit generally containing a phase comparator, a low-pass filter, and an oscillator coupled in a feedback arrangement. When an input or reference clock signal is applied to the PLL, the phase comparator compares the phase of the reference clock signal with the phase of the oscillator output signal and generates an error signal that is related to the phase relationship between the two signals. This error signal is filtered, amplified, and applied to the oscillator, thus driving the frequency of the oscillator output signal in a direction to more closely align its phase to that of the reference clock signal. When the oscillator output frequency is sufficiently close to the reference frequency, the feedback nature of the PLL causes the oscillator output to lock to the reference clock signal frequency, with the exception of some finite phase difference. This point is called the “zero phase error.” While the phases may not be aligned, their frequencies are matched such that the amount of phase difference remains substantially constant. The self-correcting nature of the PLL thus allows the system to track the frequency changes of the reference clock signal once it is locked. A frequency divider is often inserted in the feedback loop when the desired output frequency of the oscillator is some multiple of the reference clock signal frequency.
In combination with a digital phase detector, fully-digital PLLs include a digital loop filter instead of the traditional analog filter, and include a digitally-controlled oscillator instead of the voltage-controlled oscillator. In theory, these fully digital PLLs have several advantages over their analog counterparts. First, digital logic exhibits much better noise immunity than analog circuitry. Second, analog components are vulnerable to DC offset and drift phenomena that are not present in equivalent digital implementations. Further, the loop dynamics of analog PLLs are quite sensitive to process technology scaling, whereas the behavior of digital logic remains unchanged with scaling. Moreover, power dissipation is of extreme concern for portable, battery-powered, computing or communication systems. Digital PLLs reduce the power supply voltage requirements of integrated circuits.
As is known in the art, high frequency clock generation circuits such as those used in portable, electronic devices produce significant levels of electromagnetic interference (EMI). This can be particularly detrimental in portable, wireless communication applications. Consequently, manufacturers of wireless communication devices, such as cell phones, employ various techniques to reduce the EMI produced by such high frequency components. One technique employed to reduce EMI generated by a PLL clock generation circuit is to inject frequency modulation at the output of the PLL to effectively spread the frequency spectrum output and thereby affect a reduction in EMI.
FIG. 1 is a block diagram of a typical PLL 100 of the prior art using frequency modulation on its output to reduce the circuit's generation of EMI. The PLL 100 includes a phase detector 110 having a first input for the referenced clock signal and a second input for the feedback signal. The output of the phase detector 110 is coupled to the input of a digital filter 120. The output of the digital filter 120 is coupled to the input of a first adder 130, where a second input of the adder 130 receives a frequency modulation signal (fm). The frequency modulation signal (fm) is generated through a separate oscillation system. The output of multiplier 130 is coupled to the input to a digitally controlled oscillator 140, which generates an oscillated clock signal on its output. The output of digitally controlled oscillator 140 is also coupled to an input of divider 150. The output of digitally-controlled oscillator 140 is fed back to the second input of the phase detector 110 through a frequency divider 150 to operate as the feedback signal to phase detector 110.
As will be appreciated, the inherent variations in clock generation systems will cause the injected frequency modulation signal to change the average center frequency output by digitally controlled oscillator 140. Without precise synchronization of the reference clock signal and the frequency modulation signal, there may be significant fluctuations in the average clock frequency output of the digital PLL. Moreover, the added circuitry required to generate the frequency modulation signal further complicates the overall digital circuitry of the integrated circuit.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alternative digital locked loop system capable of establishing a digital frequency or phase locked loop output clock having frequency modulation without altering the average system frequency output and with minimal added complexity.
In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced.